Modern digital devices operate asynchronously from one another for maximum efficiency. Interfaces for communications between devices, therefore, require synchronizing circuits which receive the digital pulses from an external device and synchronize the pulses with an internal clock. For example, peripheral controllers for disk drives and other system components must communicate with the drive and a host computer, both of which operate asynchronously from the controller with differing data transfer rates. Commands and data transferred from the host must be synchronized for use within the disk controller for interpretation or storage prior to transfer to the disk drive.
Most current disk controllers use a buffer memory for temporary storage of data transferred between the disk drive and the host computer. To accommodate differing data transfer band width between the buffer memory and the host computer or disk drive, a first-in first-out (FIFO) sub-buffer is typically used. Using communication between the host computer and the peripheral controller as an example, transfer of data from the FIFO to the host computer is accomplished under the control of a READ or WRITE signal issued by the host. This signal is asynchronous to the internal clock of the peripheral controller. Transfer from the buffer memory to the FIFO is accomplished synchronously in the controller. In coordinating the data transfer, the controller must monitor the number of data bytes present in the FIFO. Most prior art systems employ an UP/DOWN counter which synchronously monitors the circular pointers of the FIFO.
The number of bytes present in the FIFO as indicated by the counter is then interpreted by the controller for communication control with the host. However, due to basic latency in the circuit, with one pointer changing asynchronously the number of bytes actually present in the FIFO may not be properly indicated by the counter resulting in inaccurate control of the transfer and the potential underrun or overrun of the FIFO by the host, depending on the direction of transfer. Data may therefore be lost in the overrun or underrun condition.
FIFOs must, therefore, be designed with greater depth and control of the transfer initiated with more bytes remaining in the FIFO to avoid the overrun/underrun conditions.
To reduce the oversizing requirements for the FIFO, it is desirable to synchronize the incoming READ or WRITE pulse from the host with the minimum latency to provide the greatest accuracy in the counter. Prior-art pulse synchronizers are typically constructed either of phase lock loops, which are complex and sensitive to periods of no input, or of single or multiple serial flip-flops to capture and synchronize the incoming asynchronous pulse. In this arrangement, the first flip-flop samples the input for the asynchronous pulse and, if the input has fully transitioned, then the output of flip-flop will transition. Subsequent serial flip-flops determine the width of the desired output pulse and reset the circuit. These prior-art designs are sensitive, however, to varying input pulse width and pulses which occur very near the internal clock pulse strobing the flip-flops.
Further, design of such prior-art devices normally is limited by the Nyquist criterion requiring the internal clock rate to be greater than two times the incoming asynchronous data transfer rate.